Memory bandwidth is the rate at which information may be read from or saved into a semiconductor memory by a processor. Memory bandwidth is usually expressed in items of bytes/second, although this may range for programs with natural information sizes that are not a a number of of the generally used 8-bit bytes. Memory bandwidth that's advertised for a given memory or system is normally the maximum theoretical bandwidth. In apply the noticed memory bandwidth shall be less than (and is guaranteed not to exceed) the advertised bandwidth. A wide range of laptop benchmarks exist to measure sustained memory bandwidth using a wide range of entry patterns. These are meant to supply perception into the memory bandwidth that a system ought to maintain on numerous lessons of actual applications. 1. The bcopy convention: counts the amount of information copied from one location in memory to a different location per unit time. For example, copying 1 million bytes from one location in memory to a different location in memory in one second would be counted as 1 million bytes per second.

The bcopy convention is self-constant, but is just not simply extended to cover cases with more complex entry patterns, for instance three reads and one write. 2. The Stream convention: sums the amount of information that the applying code explicitly reads plus the quantity of information that the application code explicitly writes. Using the previous 1 million byte copy example, the STREAM bandwidth could be counted as 1 million bytes learn plus 1 million bytes written in one second, for a total of two million bytes per second. The STREAM convention is most immediately tied to the person code, however could not depend all the info traffic that the hardware is actually required to perform. 3. The hardware convention: counts the actual amount of information learn or written by the hardware, whether the info movement was explicitly requested by the consumer code or not. Utilizing the identical 1 million byte copy example, the hardware bandwidth on laptop systems with a write allocate cache coverage would include an extra 1 million bytes of visitors because the hardware reads the target array from memory into cache before performing the shops.

This gives a total of three million bytes per second really transferred by the hardware. The hardware convention is most directly tied to the hardware, but may not characterize the minimum amount of data site visitors required to implement the user's code. Quantity of knowledge transfers per clock: Two, in the case of "double information charge" (DDR, DDR2, DDR3, DDR4) memory. Memory bus (interface) width: Every DDR, DDR2, or DDR3 memory interface is sixty four bits huge. Number of interfaces: Modern private computers usually use two memory interfaces (twin-channel mode) for an efficient 128-bit bus width. This theoretical most memory bandwidth is referred to because the "burst charge," which will not be sustainable. The naming convention for DDR, DDR2 and DDR3 modules specifies either a maximum speed (e.g., DDR2-800) or a most bandwidth (e.g., PC2-6400). The pace rating (800) isn't the maximum clock pace, Memory Wave however twice that (due to the doubled information price).

The specified bandwidth (6400) is the maximum megabytes transferred per second utilizing a 64-bit width. In a dual-channel mode configuration, this is effectively a 128-bit width. Thus, the memory configuration in the instance may be simplified as: two DDR2-800 modules working in twin-channel mode. Two memory interfaces per module is a common configuration for Pc system memory, but single-channel configurations are widespread in older, low-finish, Memory Wave or low-power gadgets. Some personal computers and most trendy graphics cards use greater than two Memory Wave Experience interfaces (e.g., 4 for Intel's LGA 2011 platform and the NVIDIA GeForce GTX 980). Excessive-performance graphics playing cards operating many interfaces in parallel can attain very excessive complete memory bus width (e.g., 384 bits within the NVIDIA GeForce GTX TITAN and 512 bits within the AMD Radeon R9 290X using six and eight 64-bit interfaces respectively). In programs with error-correcting memory (ECC), the extra width of the interfaces (typically seventy two reasonably than sixty four bits) isn't counted in bandwidth specs as a result of the extra bits are unavailable to store consumer knowledge. ECC bits are higher regarded as a part of the memory hardware reasonably than as data stored in that hardware.